Datencacheanalyse für einen zeitlich vorhersagbaren Prozessor

Hard real-time systems are characterized by the fact that their correctness does not only depend on the computational results but also on their timely delivery.
Therefore, the timing behavior of such systems must be known a-priori.
It is the task of WCET-analysis to compute safe upper bounds of real-time tasks, considering the possible paths through a program and a model of the underlying hardware.

In the T-CREST project, a platform for time-predictable multi-core embedded systems was developed. At TU Wien, the research groups of Prof. Puschner and Prof. Knoop jointly developed the compiler infrastructure for the time-predictable processor of this platform.

The compiler is based on the LLVM framework. A toolkit, platin, for the integration of the compiler with timing analysis has been developed (implementation langage Ruby).
The goal of this thesis is to extend the toolkit by data cache analysis capabilities.
It will be necessary to improve the existing framework to extract information about potential targets for memory accesses. Based on this information, state-of-the-art and novel techniques for data cache analysis should be implemented in platin.

Following skills are required:

Proficiency in C++ and Ruby
Basic knowledge of real-time systems, compiler construction and program analysis
Experience with the LLVM framework (optional)

Weitere Informationen

Unternehmen

Thesius Inspiration

Abschlussart

Bachelorarbeit / Masterarbeit / Dissertation

Ansprechpartner/in

Name: Herr Thesius Kontakt
E-Mail: support1@thesius.de
Tel.: keine Nummer angegeben

Branche

Elektrotechnik

Zusatzinformationen

TU Wien
Puschner, Peter; Ao.Univ.Prof. Dipl.-Ing. Dr.techn.